PLab0 — Setup & First Run
Install/verify the assembler and toolchain, run a first program, and confirm your workflow before starting the main programming labs.
Open PLab0Programming and Modeling RISC-V on RISC-V
This material presents a progressive set of laboratory sessions covering RISC-V assembly programming, debugging, macro-based abstraction, and hardware modeling using Verilog HDL. Each lab focuses on hands-on examples where execution time is measured and speedups are analyzed across scalar, vector, and multicore execution modes.
Table of Contents (Overview)
- Introduction, resources, and book organization
- Part 1 – RISC-V base assembly instruction set
- PLab0 – Setup & tooling warm-up
- PLab1 – Core RISC-V assembly programming
- PLab2 – Debugging with as, ld, and GDB
- PLab3 – Programming with macros
- Part 2 – Modeling and simulation with Verilog HDL
- MLab1–MLab4 – Building and extending RISC-V processor models
Laboratory Sessions
PLab1 — RISC-V Assembly Programming
Core instruction formats, arithmetic, control flow, functions, recursion, floating-point, and vector extensions.
Open PLab1PLab2 — Assembly, Linking & Debugging
Using as, ld, and GDB: step-by-step debugging, I/O, and multi-function programs.
Open PLab2PLab3 — Macro Programming
Macro-based abstraction for arithmetic, multiplication, and power functions.
Open PLab3MLab1 — Verilog Modeling Basics
Verilog HDL fundamentals, testbenches, ALU and RAM modules.
Open MLab1MLab2 — Simple RISC-V Model
Writing a minimal RV32I processor and associated testbenches.
Open MLab2MLab3 — Complete RV32I Architecture
Full processor design: ALU, decoder, branch unit, memory, and top-level integration.
Open MLab3MLab4 — RV32IM Extension
Extending the processor with the M extension for multiplication and division.
Open MLab4