Spec → Chisel 3 or SystemVerilog project

RISC-V Chisel & Verilog Forge

Paste a core description in JSON, YAML or plain words and pick the output. Chisel forge writes Chisel 3 modules with chiseltest tests, a pinned sbt build and a SystemVerilog emitter. Verilog forge writes synthesizable SystemVerilog directly, with Verilator testbenches and a Makefile. Either way you get design notes and download the whole project as a .zip. It runs on your own Anthropic API key, billed to your API account.

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Model Effort Stop when spend reaches (USD)

Prices are per million input / output tokens. The key goes only from this browser to api.anthropic.com. It never reaches the page author or any other server. Opus 5.5 at high effort is the recommended setting for RTL. Haiku is cheap but is likely to need several fix rounds.

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Architecture description

YAML

Load an example:

Format is detected as you type. Claude reads your original text, so comments in YAML carry through.

What the page read

parsed locally

RV32IM_Zicsr

Project options

Scala package Top-level module

Also ask Claude for a draft SystemVerilog preview of the top module (a hand translation for reading, not compiler output)

Generate

Steps: plan the modules and their interfaces, write each RTL file in dependency order, write the tests against the RTL, then write the design notes.

Fix from a compiler or test log

Paste the output of sbt test. Claude picks the files at fault and rewrites them. Tests are only changed when the log shows the test itself is wrong.